1. Field of the Invention
The present invention generally relates to a sputtering apparatus and its method of use for forming thin films in fabrication of thin film semiconductor devices.
2. Description of the Related Art
Sputtering is used to deposit thin metal and insulating films onto semiconductor wafers. As shown in FIG. 1A, a prior art magnetron sputtering apparatus 10 generally includes a vacuum chamber 11 housing a target plate 12 mounted on a cathode 15, in which the target 12 contains the metal or other material to be deposited. The target 12 is placed in a plane parallel to a substrate wafer 13 mounted on a wafer holder 14, which is the anode. The cathode 15 is connected to power supply (not shown). An inert ionizable gas, such as argon, is introduced into the vacuum chamber 11 as indicated in FIG. 1A. A plasma is generated between the electrodes (14, 15), and a bias is applied between the electrodes (14, 15) to draw the ionized gas atoms to the target 13. The ionized gas atoms bombard the target 12. As a result of the impact of the ions, a physical erosion mechanism occurs in which atoms are dislodged from the surface 12a of a target material. The dislodged particles settle on exposed surfaces inside the chamber 11, including the surface 13a of the wafer 13 mounted opposite the target 12, where they bond to the wafer surface 13a.
The sputtered particles 16 are ejected from the target surface 12a in scattered directions including trajectories that are substantially perpendicular as well as those that are oblique to the wafer surface as indicated by the arrows in FIG. 1A. The scattered trajectories 16 of the sputtered particles can create a problem in sputter processing for contacting and completely covering the bottom surfaces of via holes or other non-planar features of a wafer surface, especially in the context of filling high aspect contact holes and vias with contact and barrier metal layers. The aspect ratio is the ratio of the depth to diameter of the surface feature. The accumulation of sputtered material on the side walls of a feature, such as a via hole, prematurely closes off access to the bottom surface of the feature before it is entirely coated.
As a counter-measure to this problem, sputtering systems have positioned a collimator 17 between the target surface 12a and the wafer surface 13a to be processed. The collimator 17 has a plurality of closely packed, substantially parallel passages or unit cells 18 formed through the thickness of a solid grid or plate forming walls 19 bounding the passages 18. For instance, as illustrated in FIGS. 1B and 1C, the collimator 17 can have a honeycomb structure made of sheet metal. The passages 18 have a suitable length to diameter ratio (i.e., the collimator aspect ratio) such that the angle .theta. delimited from one point on one end of a passage to another point on the opposite side of the opening end of the same passageway will define the maximum trajectory angle that a particle could have without striking the collimator 17. As can be better seen in FIG. 1D, the collimator 17 functions as a filter of sorts to effectively permit only the sputtered particles 16 within a given range of trajectories to pass through the effective open area of one of its passages 18 and deposit upon the wafer surface 13a.
As illustrated in FIGS. 1E-1H, during sputtering, sputtered particles accumulate on exposed surfaces of the collimator 17, among other exposed surfaces within vacuum chamber 11, leading to a build-up 101 on the walls 19 bounding the passages 18. FIGS. 1F-1H show the result of the ions that hit the collimator 17 and stick to it. They do not possess enough energy to migrate/diffuse to other areas, and stay where they hit the collimator 17. This causes deposited material 101 to build up on the collimator and reduce the cross sectional area of the passages 18. As FIGS. 1F-1H show, this is especially bad because the collimator openings are generally hexagonal or circular, and hole closure consequently occurs in two dimensions. For instance, a 10 percent decrease in hole diameter of passage 18 results in a decrease in transmission of 19 percent, a 20 percent decrease in hole diameter results in a 36 percent transmission decrease. The greatest accumulation of intercepted ions at the collimator 17 tends to occur adjacent the target side, or entrance, of the collimator passages 18. This accumulation reduces the effective open area of the passages (unit cells) 18. For example, FIG. 1E shows the clean original collimator, while FIGS. 1F and 1G show progressively greater build-up 101 to leave only 30-50% and &lt;10% open area, respectively, in cell 18 as the collimator's service life progresses. FIG. 1H is a top view of cell 18 at the various stages of use depicted in FIGS. 1E-1G.
As result of such build-up 101 on the collimator 17, the deposition rate of sputtered particles onto the wafer 13 decreases over time requiring longer deposition times to compensate for the diminishing transmission such that the collimator 17 must be periodically cleaned or even replaced to restore acceptable deposition rates and/or uniformity. Also, the passageways 18 of the collimators tended to fill and clog up unevenly, resulting in the need to shorten processing times between cleaning cycles or replace the collimator before it was fully used.
Another problem associated with the build-up 101 is that the molecules blocked by the collimator 17 transfer their kinetic and thermal energy to the collimator 17. This causes the collimator to heat-up. The collimator 17 will then radiate heat to the substrate 13, which can adversely affect the properties of the deposited film. Substrate cooling may not be adequate to protect the substrate from thermal damage by collimator radiation. If this is the case, then the sputter power must be decreased, which increases deposition times and costs. Irregular heating of the collimator can also cause particulate formation, because of flaking off of deposited material from the collimator surface. The present inventors are unaware of any conventional technique available to cool a collimator in service without interrupting processing.
Yet another problem with prior collimator designs has been that it has not been possible to measure the extent of passageway blockage or build-up without stopping processing to access the collimator for an inspection. Yet another problem associated with conventional collimator arrangements has been the difficulty, if not impossibility, in measuring or controlling collimator temperature without interrupting production in order to run cooling gases through the chamber. That mode of cooling the collimator off-line also contributed to reductions in tool throughput and could prove inadequate, especially if the collimator temperature rose above desired levels during a single deposition.
The overall down time incurred due to the frequent cleaning maintenance and/or collimator cooling required of prior collimator designs has represented substantial lost production time (i.e., reduced wafer throughput) during tool downtimes and increased maintenance costs, In any event, despite such prior efforts, the service lifetime of the prior collimators still is often considerably less than that of the sputter targets used in semiconductor processing, to further increase down time and processing disruptions.
Efforts to reduce the down times and concomitant losses in productivity associated with servicing collimators have included cleaning the collimator without breaking the vacuum in the chamber, such as proposed in the prior collimator design of U.S. Pat. No. 5,409,587. U.S. Pat. No. 5,393,398 teaches a magnetron sputtering apparatus using a target of a diameter no smaller than that of the wafer and not greater than 1.4 times that of the wafer in order to increase the proportion of sputtered particles reaching the wafer perpendicularly and reduce build-up at the collimator passageways. U.S. Pat. No. 5,393,398 also teaches use of a particle interceptor capable of being rotated so that the shadow of the particle interceptor changes continuously relative to the surface of the wafer. Japanese published application no. 07-316808 teaches rotating the collimator in conjunction with use of a mechanism to vibrate the rotational drive shaft of the collimator in a direction parallel to the substrate. U.S. Pat. No. 5,643,428 teaches use of a multi-tiered collimator system to reduce localized build-up. As other prior approaches to reducing the rate of build-up in collimator passageways, U.S. Pat. No. 5,223,108 teaches using tapered collimator passageways, while U.S. Pat. No. 5,223,108 teaches using a collimator having an array of passageways of varied diameters such that the hole radii are smaller in regions having a higher vertical flux component than in regions having lower vertical flux components.
However, prior to the present invention, the semiconductor industry still had need for a collimator cleaning/servicing arrangement which could be executed without requiring that the wafer processing operations be temporarily halted.